{"id":13765,"date":"2025-03-20T04:10:43","date_gmt":"2025-03-20T04:10:43","guid":{"rendered":"https:\/\/bvcoend.ac.in\/?page_id=13765"},"modified":"2026-03-18T05:52:09","modified_gmt":"2026-03-18T05:52:09","slug":"vhdl-programming-lab-ece","status":"publish","type":"page","link":"https:\/\/bvcoend.ac.in\/index.php\/vhdl-programming-lab-ece\/","title":{"rendered":"VHDL Programming Lab(ECE)"},"content":{"rendered":"[vc_row][vc_column width=”1\/4″][vc_wp_custommenu title=”Imp Links” nav_menu=”73″][\/vc_column][vc_column width=”3\/4″][vc_column_text]\n

VHDL PROGRAMMING LAB<\/span><\/h3>\n

Introduction<\/span><\/h3>\n

The VHDL Programming Lab is designed to provide students with hands-on experience in digital circuit design using VHDL (VHSIC Hardware Description Language). This lab serves as a foundation for understanding hardware modeling, simulation, and synthesis of digital circuits. Students will explore the implementation of combinational and sequential logic circuits, both synchronous and asynchronous, through simulation and practical applications. By working with industry-standard tools, students will gain essential skills for hardware description, verification, and FPGA-based design, preparing them for careers in VLSI design and digital hardware development.<\/span><\/p>\n

Course Objectives<\/span><\/h3>\n\n\n\n\n\n\n
COB-1<\/strong><\/span><\/td>\nTo provide knowledge of basics of VHDL Programming<\/span><\/td>\n<\/tr>\n
COB-2<\/strong><\/span><\/td>\nTo impart knowledge of Combinational logic circuit simulation and its implementation.<\/span><\/td>\n<\/tr>\n
COB-3<\/strong><\/span><\/td>\nTo impart knowledge of simulation and implementation of Synchronous Sequential logic circuit.<\/span><\/td>\n<\/tr>\n
COB-4<\/strong><\/span><\/td>\nTo impart knowledge of simulation and implementation of Asynchronous Sequential logic circuit.<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Course Outcomes<\/span><\/h3>\n\n\n\n\n\n\n\n\n
CO<\/span><\/th>\nStatement<\/span><\/th>\nBloom’s Level<\/span><\/th>\n<\/tr>\n<\/thead>\n
ECE306T.1<\/strong><\/span><\/td>\nUnderstand the basics of VHDL Programming and its constituents<\/span><\/td>\nUnderstand, Remember<\/span><\/td>\n<\/tr>\n
ECE306T.2<\/strong><\/span><\/td>\nImplement and analyze the functionality of Combinational logic circuit<\/span><\/td>\nApply, Analyze<\/span><\/td>\n<\/tr>\n
ECE306T.3<\/strong><\/span><\/td>\nDesign and evaluate implementation of Synchronous Sequential logic circuit<\/span><\/td>\nEvaluate, Create<\/span><\/td>\n<\/tr>\n
ECE306T.4<\/strong><\/span><\/td>\nDesign Asynchronous Sequential logic circuit and understanding of programable devices<\/span><\/td>\nCreate, Understand<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

CO-PO-PSO Mapping<\/span><\/h3>\n\n\n\n\n\n\n\n\n
CO\/PO<\/span><\/th>\nPO1<\/span><\/th>\nPO2<\/span><\/th>\nPO3<\/span><\/th>\nPO4<\/span><\/th>\nPO5<\/span><\/th>\nPO6<\/span><\/th>\nPO7<\/span><\/th>\nPO8<\/span><\/th>\nPO9<\/span><\/th>\nPO10<\/span><\/th>\nPO11<\/span><\/th>\nPO12<\/span><\/th>\nPSO1<\/span><\/th>\nPSO2<\/span><\/th>\n<\/tr>\n<\/thead>\n
ECE306T.1<\/strong><\/span><\/td>\n3<\/span><\/td>\n2<\/span><\/td>\n<\/td>\n<\/td>\n2<\/span><\/td>\n<\/td>\n<\/td>\n<\/td>\n1<\/span><\/td>\n1<\/span><\/td>\n<\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n1<\/span><\/td>\n<\/tr>\n
ECE306T.2<\/strong><\/span><\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n3<\/span><\/td>\n2<\/span><\/td>\n2<\/span><\/td>\n<\/td>\n<\/td>\n<\/td>\n1<\/span><\/td>\n1<\/span><\/td>\n<\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
ECE306T.3<\/strong><\/span><\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n3<\/span><\/td>\n2<\/span><\/td>\n2<\/span><\/td>\n<\/td>\n<\/td>\n<\/td>\n1<\/span><\/td>\n1<\/span><\/td>\n<\/td>\n<\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n<\/tr>\n
ECE306T.4<\/strong><\/span><\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n3<\/span><\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n<\/td>\n<\/td>\n<\/td>\n1<\/span><\/td>\n1<\/span><\/td>\n<\/td>\n2<\/span><\/td>\n3<\/span><\/td>\n3<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

<\/h3>\n

\"\"Facilities<\/span><\/h3>\n

Operating System \/ Software<\/span><\/h4>\n\n\n\n\n\n\n\n
Sr. No.<\/span><\/th>\nName<\/span><\/th>\nVersion<\/span><\/th>\n<\/tr>\n<\/thead>\n
1.<\/span><\/td>\nWindows<\/span><\/td>\n10<\/span><\/td>\n<\/tr>\n
2.<\/span><\/td>\nSiemens (Mentor Graphics) HEP1-Questa<\/span><\/td>\n2019<\/span><\/td>\n<\/tr>\n
3.<\/span><\/td>\nVivado<\/span><\/td>\n2019<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Hardware<\/span><\/h4>\n\n\n\n\n\n\n\n\n\n
Sr.No.<\/span><\/th>\nEquipment Name<\/span><\/th>\nSpecification<\/span><\/th>\nQuantity<\/span><\/th>\n<\/tr>\n<\/thead>\n
1.<\/span><\/td>\nComputer<\/span><\/td>\nIntel Core i9 10 Gen 2.10 GH 32 GB RAM<\/span><\/td>\n1<\/span><\/td>\n<\/tr>\n
2.<\/span><\/td>\nComputer<\/span><\/td>\nIntel Core i5 4 Gen 2.10 GH 16 GB RAM<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
3.<\/span><\/td>\nComputer<\/span><\/td>\nIntel Core i7 8 Gen 3.10 GH 8 GB RAM<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
4.<\/span><\/td>\nComputer<\/span><\/td>\nIntel Core i5 10 Gen 2.10 GH 8 GB RAM<\/span><\/td>\n27<\/span><\/td>\n<\/tr>\n
5.<\/span><\/td>\nPrinter<\/span><\/td>\nHP Laser Jet Pro P1108 Plus<\/span><\/td>\n01<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Staff<\/span><\/h3>\n
    \n
  • Lab Incharge:<\/strong> Dr. Manoj Sharma<\/span><\/li>\n
  • Other Faculty Members:<\/strong> Dr. Yogita Arora and Dr. Jyoti Gupta<\/span><\/li>\n
  • Lab Assistant:<\/strong> Mr. Deepanshu<\/span><\/li>\n<\/ul>\n[\/vc_column_text][\/vc_column][\/vc_row]\n","protected":false},"excerpt":{"rendered":"

    [vc_row][vc_column width=”1\/4″][vc_wp_custommenu title=”Imp Links” nav_menu=”73″][\/vc_column][vc_column width=”3\/4″][vc_column_text] VHDL PROGRAMMING LAB Introduction The VHDL Programming Lab is designed to provide students with hands-on experience in digital circuit design using VHDL (VHSIC Hardware Description Language). This lab serves as a foundation for understanding hardware modeling, simulation, and synthesis of digital circuits. Students will explore the implementation of combinational…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/13765"}],"collection":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/comments?post=13765"}],"version-history":[{"count":8,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/13765\/revisions"}],"predecessor-version":[{"id":15726,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/13765\/revisions\/15726"}],"wp:attachment":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/media?parent=13765"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}