{"id":2638,"date":"2020-01-29T05:27:10","date_gmt":"2020-01-29T05:27:10","guid":{"rendered":"https:\/\/bvcoend.ac.in\/?page_id=2638"},"modified":"2026-03-14T04:39:17","modified_gmt":"2026-03-14T04:39:17","slug":"switching-theory-and-logic-design-lab","status":"publish","type":"page","link":"https:\/\/bvcoend.ac.in\/index.php\/switching-theory-and-logic-design-lab\/","title":{"rendered":"DIGITAL SYSTEM DESIGN LAB"},"content":{"rendered":"[vc_row][vc_column width=”1\/4″][vc_wp_custommenu title=”Imp Links” nav_menu=”68″][\/vc_column][vc_column width=”3\/4″][vc_column_text]Lab Room No:<\/strong>\u00a0A308<\/span>
\nLab In charge:<\/strong> Dr. K.Sudha<\/span>
\nLab Attendant:<\/strong> Mr. Sachin<\/span>
\nLab Subjects:<\/strong> Digital System Design Lab-(EEE-338P)<\/span><\/p>\n

\"\"<\/span><\/p>\n

About\u00a0<\/strong>Lab:<\/b><\/span><\/p>\n

Digital system design using VHDL (VHSIC Hardware Description Language) in a laboratory setting allows students and engineers to develop and test digital circuits through simulation and synthesis. In the laboratory, VHDL is used to describe the behaviour and structure of digital systems, from simple gates to complex microprocessors. The hands-on approach provides experience with writing VHDL code, simulating designs to check for functionality, and synthesizing the code to generate hardware implementations. By using software tools such as ModelSim or Xilinx ISE, designers can simulate their circuits, debug them, and prepare them for physical realization on FPGAs (Field-Programmable Gate Arrays). This practical experience in a lab environment helps in understanding theoretical concepts, improves problem-solving skills, and prepares individuals for real-world hardware design challenges.<\/span><\/p>\n

List of Experiment:<\/strong><\/span><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
S. No.<\/strong><\/span><\/td>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 TITLE OF LAB EXPERIMENTS<\/strong><\/span><\/td>\nCO<\/strong><\/span><\/td>\n<\/tr>\n
1<\/span><\/td>\nDesign all gates using VHDL.<\/span><\/td>\n1<\/span><\/td>\n<\/tr>\n
2<\/span><\/td>\nDesign a half adder\/ full adder using VHDL.<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
3<\/span><\/td>\nDesign a multiplexer\/ demultiplexer using VHDL.<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
4<\/span><\/td>\nDesign a decoder\/ encoder using VHDL.<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
5<\/span><\/td>\nDesign a comparator using VHDL.<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
6<\/span><\/td>\nDesign a code converter using VHDL.<\/span><\/td>\n2<\/span><\/td>\n<\/tr>\n
7<\/span><\/td>\nDesign a flip flop using VHDL.<\/span><\/td>\n3<\/span><\/td>\n<\/tr>\n
8<\/span><\/td>\nDesign a counter using VHDL.<\/span><\/td>\n3<\/span><\/td>\n<\/tr>\n
<\/td>\nAdditional Experiments<\/strong><\/span><\/td>\n<\/td>\n<\/tr>\n
9<\/span><\/td>\nDesign a shift register using VHDL.<\/span><\/td>\n4<\/span><\/td>\n<\/tr>\n
10<\/span><\/td>\nDesign a seven segment display using VHDL.<\/span><\/td>\n4<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n[\/vc_column_text][\/vc_column][\/vc_row]\n","protected":false},"excerpt":{"rendered":"

[vc_row][vc_column width=”1\/4″][vc_wp_custommenu title=”Imp Links” nav_menu=”68″][\/vc_column][vc_column width=”3\/4″][vc_column_text]Lab Room No:\u00a0A308 Lab In charge: Dr. K.Sudha Lab Attendant: Mr. Sachin Lab Subjects: Digital System Design Lab-(EEE-338P) About\u00a0Lab: Digital system design using VHDL (VHSIC Hardware Description Language) in a laboratory setting allows students and engineers to develop and test digital circuits through simulation and synthesis. In the laboratory, VHDL…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/2638"}],"collection":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/comments?post=2638"}],"version-history":[{"count":10,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/2638\/revisions"}],"predecessor-version":[{"id":15631,"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/pages\/2638\/revisions\/15631"}],"wp:attachment":[{"href":"https:\/\/bvcoend.ac.in\/index.php\/wp-json\/wp\/v2\/media?parent=2638"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}