{"id":9291,"date":"2023-03-02T08:28:56","date_gmt":"2023-03-02T08:28:56","guid":{"rendered":"https:\/\/bvcoend.ac.in\/?page_id=9291"},"modified":"2023-03-02T08:56:55","modified_gmt":"2023-03-02T08:56:55","slug":"siemens-empower-education","status":"publish","type":"page","link":"https:\/\/bvcoend.ac.in\/index.php\/siemens-empower-education\/","title":{"rendered":"Siemens Empower Education"},"content":{"rendered":"[vc_row][vc_column][vc_tta_tour shape=”square” color=”juicy-pink” active_section=”1″ no_fill_content_area=”true”][vc_tta_section title=”About Training” tab_id=”1677746541706-290213d9-ec7d”][vc_column_text]\"\"<\/p>\n
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Register Here<\/a><\/span><\/h2>\n
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To bridge the industry academia gap in terms of skill set requirements in the area of IC design and verification technologies, Department of Electronics and Communication Engineering , <\/span>Bharati Vidyapeeth\u2019s College of Engineering (BVCOE)<\/strong>, New Delhi, has\u00a0<\/span>collaborated\u00a0<\/strong>with\u00a0<\/span>Siemens EDA<\/strong><\/span>\u00a0(<\/span>Mentor Graphics -A Siemens Business<\/span>)<\/strong>\u00a0<\/span>for training students\u00a0<\/span>on System Verilog<\/strong><\/span>. The System Verilog training material has been developed by\u00a0<\/span>North Carolina State University (NCSU), Carolina USA<\/span>\u00a0<\/strong>and\u00a0<\/span>Siemens EDA<\/strong><\/span>\u00a0funded NCSU with technical inputs for the course module. BVCOE and Siemens EDA have signed an Agreement to have access of this course module.<\/span><\/span><\/p>\n

To strengthen the training program further, for the aim of student’s placement in VLSI\/semiconductor industries, Dept of ECE has augmented the training program\u2019s content to include some of the important modules like\u00a0<\/span>Linux, Digital Design, STA, CDC, Verilog HDL, UVM, C++, C and Data Structures, CMOS along with System Verilog<\/span>.\u00a0\u00a0<\/strong>The training program also include several\u00a0<\/span>comprehensive projects<\/strong><\/span>. The training program is jointly conducted by BVCOE and M\/s 3ST Technologies Pvt. Ltd.\u00a0<\/span><\/span><\/p>\n

Dr Manoj Sharma (Associate\u00a0 Professor,\u00a0 Dept.\u00a0 ECE, BVCOE)<\/strong>\u00a0together with external industry expert,\u00a0<\/span>Mr. Sandeep Gupta (Director, 3ST Technologies, IIT Delhi Alumni)<\/strong>\u00a0train and gloom the\u00a0 students\u00a0 collaboratively, enabling\u00a0 them to\u00a0 ensure\u00a0 their\u00a0 breakthrough\u00a0 in\u00a0 VLSI\u00a0 industries. Students are trained on these skills\u00a0 up to\u00a0 the\u00a0 fullest\u00a0 quality\u00a0 as\u00a0 per industry requirements. Training-classes are conducted on Saturdays and Sundays which enable students to learn without affecting the normal academic schedule of regular-classes. The rigorous training sessions cover theoretical aspects in depth, focusing on practical implementations of the concepts.\u00a0 The course emphasis on implementing the learned techniques through dedicated examples and projects.\u00a0<\/span><\/span><\/p>\n

After completion of the \u2018Siemens Empower Education\u2019 (previously known as Mentor Graphics HEP) training program, students have the opportunity to earn free <\/span>\u2018Siemens Academic Digital Badges<\/span>\u2019<\/strong>\u00a0<\/span>from Siemens under ‘Siemens Empower Education\u2019 program.<\/span><\/span><\/p>\n

Also, students can have\u00a0<\/span>certificates from \u2018Siemens EDA Learning Services\u2019<\/span>\u00a0<\/span>which would require students to attempt a test and pass the\u00a0<\/span>test with 80%<\/span>\u00a0<\/span>and above.<\/span><\/span><\/p>\n

After completing the Placement Oriented Training on \u2018System Verification using System Verilog\u2019 under \u2018Siemens Empower Education\u00a0(Previously\u00a0Mentor Graphics HEP) Program, students are working in following companies:<\/strong><\/span><\/p>\n

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Contact<\/b>:<\/b><\/span><\/p>\n

Dr. Manoj Sharma<\/span>\u00a0<\/b><\/a>\u00a0(Associate Professor,\u00a0Bharati Vidyapeeth\u2019s College of Engineering<\/b>)<\/span><\/span><\/p>\n

E-MAIL ID:\u00a0<\/b>manoj.sharma@bharatividyapeeth.edu<\/span><\/a><\/span><\/p>\n

Office<\/b>\u00a0Phone<\/b>:<\/b>\u00a0(011) 25258637,25278443\u00a0<\/span>Extn.:<\/b>\u00a0 303\/261<\/span><\/span>[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”MOUs” tab_id=”1677746541716-2af65461-6b96″][vc_column_text]\n

The following ‘Agreements’ and ‘Memorandum of Understanding’ are signed (with external industry and BVCOE) since inception of the training .<\/span><\/p>\n

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  1. Confidential Information Exchange Agreement (CIEA) – Mentor Graphics (A Siemens Business): Mentor HEP Functional Verification Training material , Effective date 11\/12\/2018<\/span><\/li>\n
  2. 3ST Technologies Pvt Ltd, In-house Training program, Program Name: – System Verification using System Verilog (the HEP program from Mentor Graphics), dated 29 Jan 2019 ( batch 1)<\/span><\/li>\n
  3. 3ST Technologies Pvt Ltd, In-house Training program, Program Name: – System Verification using System Verilog (the HEP program from Mentor Graphics), dated\u00a06\u00a0Dec 2019 ( batch\u00a02)<\/span><\/li>\n
  4. 3ST Technologies Pvt Ltd, In-house Training program, Program Name: – System Verification using System Verilog (the HEP program from Mentor Graphics), dated\u00a010 March 2021\u00a0(batch\u00a03)<\/span><\/li>\n
  5. 3ST Technologies Pvt Ltd, In-house Training program, Program Name: – System Verification using System Verilog ( the HEP program from Mentor Graphics), dated\u00a029\u00a0Nov 2021 ( batch\u00a04)<\/span><\/li>\n
  6. 3ST Technologies Pvt Ltd, In-house Training program, Program Name: – System Verification using System Verilog ( the HEP program from Mentor Graphics), dated\u00a018 Feb 2022 ( batch\u00a05)<\/span><\/li>\n<\/ol>\n[\/vc_column_text][\/vc_tta_section][vc_tta_section title=”Placements” tab_id=”1677746690073-4121c67c-85b4″][vc_column_text]\n