Dr. Manoj Sharma 
Associate Professor 
Bharati Vidyapeeth’s College of Engineering  

E-MAIL ID: manoj.sharma@bharatividyapeeth.edu

Office Phone: (011) 25258637,25278443 Extn.:  303/261

 

Qualification: 

  • Ph.D. in Low Power VLSI Design
  • M.Tech VLSI Design
  • MBA Systems
  • PGD – Embedded Systems, VLSI Design
  • PGDGIS
  • B.Tech- EEE

Area of Specialization: 

  • VLSI Design
  • System/ Product design and implementation

Work Experience:

  • Teaching:  16+ years

Subjects Taught:

  • VLSI Front End/ Back End subjects at PG and UG level
  • Digital Communication at UG level

Patent:

  • 2 Patents application submitted in the area of VLSI Design – IPO

Professional Membership:

  • Secretary IEEE India SSCS
  • Executive Committee Member IEEE India SSCS/CASS
  • Senior Member IEEE (8 years), SSCS, VLSI, CASS, CSTC VLSI

Papers Published:

International Journals (10):

  1. Manoj Sharma, Asheesh Shah and Arti Noor, Analysis and Evaluation of Adiabatic PFAL Inverter, Volume : No.9 (2016) Issue No. :23 (2016), Pages : 299-309, International Journal of Control Theory and Applications (Scopus)
  2. Manoj Sharma, Udit Khanna and Ankita Saxena, Hardware accelerated approach for floating-point multiplication on 32-bit pipelined RISC-V processor, Volume : No.9 (2016) Issue No. :23 (2016), Pages : 265-270 International Journal of Control Theory and Applications (Scopus)
  3. Manoj Sharma, Arti Noor, “Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits”, Advances in Electronics, Volume 2015 (2015), Article ID 202131, 10 pages
    https://www.dx.doi.org/10.1155/2015/202131
  4. Manoj Sharma, Arti Noor “Modified CPL Adiabatic Gated Logic –MCPLAG based DPET DFF with XOR” International Journal of Computer Applications (0975 – 8887) Volume 89– No.19, March 2014
  5. Manoj Sharma, Arti Noor “Reconfigurable CPL Adiabatic Gated Logic –RCPLAG based Universal NAND/NOR Gate” International Journal of Computer Applications (0975 – 8887) Volume 95– No.26, June 2014
  6. Manoj Sharma and Mohammad Ayoub Khan “Investigation of Low-Power Techniques in Networkon- Chip” World Applied Sciences Journal indexed by Scopus
  7. Sharma, M.; Verma, R “Efficient handling of pps in Radix 4 Booth’s Algorithm implementation for DSP applications” International Journal of Embedded and Real-Time Communication Systems (IJERTCS)
  8. M Ayoub Khan, Manoj Sharma, Brahmanandha Prabhu R “A Survey of RFID Tags” International Journal of Recent Trends in Rngineering ( IJRTE) , Vol I, No. May 2009, ACEEE, pp 68-71https://www.www.academypublisher.com/ijrte/vol01/no04/ijrte0104068071.pdf
  9. Manoj Sharma and Arti Noor Positive Feed Back Adiabatic Logic: PFAL Single Edge Triggered Semi- Adiabatic D Flip Flop AJBAS IDOSI https://www.idosi.org/ajbas/ajbas.htm
  10. Anmol Aggarwal, Nikhilesh Chhabra, Manoj Sharma, “The Use and Impact of ICT for HEP in India”, International Symposium on Education Informatics Conference: International Conference on Advances in Computing, Communications and Informatics

National Journal (1):

  1. Manoj Sharma, Ankur Sangal, Bharat Singh “Validation techniques for Integrated Circuit (IC) Layout” Proceedings of Annual Seminar on CDAC Noida Technologies, Noida, India March-2011 pp 42-49 , ISBN 9788191016710

International Conference (17):

  1. Manoj Sharma and Arti Noor “CPL-Adiabatic Gated logic (CPLAG) XOR gate” International Conference on Advances in Computing, Communications and Informatics – ICACCI-2013, August 22-25, 2013
  2. Arun Kumar, Manoj Sharma “Design and analysis of 2:1 multiplexer using adiabatic techniques ECRL and PFAL” International Workshop on Advances in VLSI Circuit Design and ECAD Tools (AVCDCT13)
  3. International Conference on Advances in Computing, Communications and Informatics – ICACCI-2013, August 22-25, 2013
  4. Ashmeet, Manoj Sahrma “Basic Gates Implementation Using ECRL and PFAL”, International
  5. Conference on Advances in Computing, Communications and Informatics – ICACCI-2013, August 22- 25, 2013
  6. Manoj Sharma and K.S.Chari “Integrated Circuit Layout Design Screening” 2013 IEEE Conference on Information and Communication Technologies(ICT 2013) 11-12 April 3013 https://www.ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6558303&abstractAccess=no&userType=inst
  7. Manoj Sharma and K.S.Chari “Custom Tools for IC LD Evaluation” 2013 IEEE Conference on Information and Communication Technologies(ICT 2013) 11-12 April 3013 https://www.ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6558302&abstractAccess=no&userType=inst
  8. Sharma, M.; Khan, M.A “Energy and power issues in Network-on Chip” Information and Communication Technologies (WICT), 2011 World Congress on Digital Object Identifier: 10.1109/WICT.2011.6141441 Publication Year: 2011 , Page(s): 1328 – 1333 https://www.ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6141441&url=%2Fstamp%2Fstamp.jsp%3Ftp%3D%26arnumber%3D6141441
  9. Sharma, M.; Verma, R. “Disposition (reduction) of (negative) partial product for Radix 4 Booth’s Algorithm” Information and Communication Technologies (WICT), 2011 World Congress on Digital Object Identifier: 10.1109/WICT.2011.6141414 Publication Year: 2011 , Page(s): 1169 – 1174 https://www.ieeexplore.ieee.org/search/searchresult.jsp?newsearch=true&queryText=modified+booths+algo+manoj+wict+2011&x=48&y=17
  10. Dr. K S Chari, Manoj Sharma “Assessment and Comparison of IC Layout Designs” – 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN) https://www.www.niece.in/wp-content/uploads/2011/05/Accepted-List.pdf (Conference to be held on 21-22 July 2011 )
  11. Manoj Sharma, Arti Noor, Satish Chandra Tiwari,. Kunwar Singh “An Area and Power Efficient Design of Single Edge Triggered D Flip Flop” – International Conference on Advances in Recent Technologies in Communication and Computing, 2009. ARTCom ’09. Issue Date: 27-28 Oct. 2009 On page(s): 478 – 481, https://www.ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=5329294&tag=1b
  12. M Ayoub Khan, Manoj Sharma, Brahmanandha Prabhu R “FSM based FMO and Miller encoder for UHF RFID Tag Emulator” – 2009 IEEE International Advance Computing Conference (IACC 2009) Patiala, India, 6-7 March 2009 https://www.ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04809207
  13. M Ayoub Khan, Manoj Sharma, Brahmanandha Prabhu “FSM based Manchester Encoder for UHF RFID Tag Emulator” Proceedings of the 2008 International Conference on Computing, Communication and Networking (ICCCN 2008) https://www.ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04787699
  14. Arti Noor, Manoj Sharma, Kunwar Singh, Satish Chandra Tiwari, “An Area and Power Efficient Design of Single Edge Triggered D Flip Flop” NCVESCOM 09 – National Conference on VLSI,
  15. Embedded Systems, Signal Processing and Communication Technologies 26th -27th March 2009
  16. Semi Adiabatic ECRL and PFAL Full Adder Subhanshi Agarwal and Manoj Sharma, The Fourth
  17. International workshop on VLSI (VLSI 2013)- Third International Conference on Advances in Computing & Information Technology (ACITY 2013), July 27, 2013, Chennai, India, https://www.airccse.org/currentissue12.html, https://www.airccj.org/CSCP/vol3/csit3418.pdf

 

Seminar/Conference/FDP/Workshop Attended:

  1. Participated FDP on Networking Simulation using NetSim on 17th April 2017
  2. IEEE Technical Activities Volunteer Training workshop on 19 Jan 2015
  3. IEEE Conference Organizers workshop (COW15) on 25 April 2015
  4. Institutional Accreditation and Management – Short term course at National Institute of Technical Teachers Training and Research , Media and Continuing Education Center
  5. Workshop on Analog and Mixed Signal Design by Eminent Professor Bram Nauta, University of Twente, Netherland, 30, 31 Oct 2012, IEEE Solid State Circuits Society (IEEE-SSCS), Delhi Chapter, STMicroelectronics india
  6. From millibits to Terabits per second and Beyond Over 60 years of Innovation – Distinguished Lecture, by Prof. Renuka P. Jindal, University of Louisiana, IEEE-EDS-SSCS Delhi Chapter STMicroelectronics india December 2012
  7. Analog Electronics -Workshop at MAIT, via National Mission on Education through Information and Communication Technology, Indian Institute of Technology, Kharagpur 4th June – 14th June 2013
  8. Analog & Mixed Signal Design and Test , High Performance Computer Architecture- Seminar by Dr. Shouribrata Chatterjee (IIT Delhi) – Today’s challenges in Analog and Mixed Signal Design; Prof. Virendra Singh (IIT Bombay) – Challenges in high performance computer architecture, Architecting energy efficient reliable systems; Mr. Sanchit Bhatia (Agilent Technologies)- Latest Trend in Test & Measurement for Analog & Mixed Signal Domain, IEEE Solid State Circuits Society (IEEE-SSCS), Delhi Chapter, STMicroelectronics india, 21st of June 2013

Awards or Books Published:

  1. Book- Design and Modeling of Low Power VLSI system,ISBN 10: 1522501908  ISBN 13: 9781522501909, Publisher: IGI Global, 2016,
  2. Winner IEEE SSCS membership 2013

Other Activities:

  1. Guest of Honor, to inaugurate the IEEE Conference on Emerging Devices and Smart Systems (ICEDSS2017). Technical Talk on ‘Wearable Technologies’ on 3rd March 2017 during the IEEE Conference on Emerging Devices and Smart Systems ( ICEDSS2017)
  2. Advisory Board- Advances in Information Quality and Management, IGI Global book series are submitted to SCOPUS
  3. Advisory boards/Technical Committee for many journals and conferences
  4. Organized International Event in Singapore – SS : Methodologies for VLSI System Optimization and Recent Advances in association with IEEE TENCON2016, Technologies for Smart Nation, Singapore, 22-25 November 2016 (selected papers published in IEEE xplore) 
  5. Organized International Event- Special Track on “Recent Technological Developments in VLSI Design and Tool Automation”,18-19 Nov 2016(selected papers published in IEEE xplore)
  6. Organized International Event- International Workshop on Advances in VLSI Circuit Design and CAD Tools (AVCDCT15) (selected papers published in IEEE xplore)
  7. Organized International Event- International Workshop on Advances in VLSI Circuit Design and CAD Tools (AVCDCT14) (selected papers published in IEEE xplore)
  8. Organized International Event- Special Track on “Recent Technological Developments in VLSI Design and Tool Automation 2014 (selected papers published in IEEE xplore)
  9. Organized International Event- International Workshop on Advances in VLSI Circuit Design and CAD Tools (AVCDCT13) (selected papers published in IEEE xplore)
  10. Organized International Event- IEEE Tutorial on “Essence of Power Aware CMOS Design and Techniques used” 2013
  11. Organized National Workshop- National Workshop on Analog IC Design in association with IEEE India SSCS and technically sponsored by IEEE CASS
  12. Inaugural Convenor for BVCOE IEEE SSCS student sub committee
  13. Volunteer Continuous contribution to Research community as, event organizer, TPC Chair, Session Chair, PC member, Reviewer to international Journals and Conferences