Introduction
The Logic Design and Analysis using Verilog Lab is designed to equip students with hands-on experience in digital system design using Verilog HDL. This lab focuses implementing digital designs using Verilog HDL, synthesis and FPGA. Students will learn to model, simulate, and verify digital circuits using industry-standard tools, preparing them for careers in VLSI design and hardware development.
Course Objectives:
- Learn and understand the architectures of Field-programmable Gate Arrays.
- Translate a software application into hardware logic for FPGA architectures
- Design synthesizable systems based on industry-standard coding methods
- Build testbenches and create data models to verify bit-true accurate designs.
Facilities
The Verilog Lab is equipped with the following hardware and software resources:
Hardware Resources:
- Computer Systems:
- Intel Core i9 10th Gen 2.10 GHz, 32 GB RAM (1 unit)
- Intel Core i5 4th Gen 2.10 GHz, 16 GB RAM (2 units)
- Intel Core i7 8th Gen 3.10 GHz, 8 GB RAM (2 units)
- Intel Core i5 10th Gen 2.10 GHz, 8 GB RAM (27 units)
- Printer: HP Laser Jet Pro P1108 (1 unit)
- ZYBO Board Zybo+Accessory Kit (410-279) (2 units)
- ZED Board Zed Board (410-248) (1 units)
Software Resources:
- Siemens Mentor Graphics Tanner HEP-2 ( QuestaSim )
Staff
- Lab Incharge: Dr Manoj Sharma
- Lab Assistant: Ms. Asha Saini