The Digital System Design lab provides the experimental platform for the students to code and implement the RTL level design using VHDL language and modern CAD tools. In this lab, students design and implement various combinational and sequential circuits starting from low-level modules such as AND, OR gates to high-level modules such as adders, decoders, multiplexer, ALU etc. The prerequisite for this lab is a complete understanding of digital electronics.

Objective of the Laboratory:

  • To understand the basic concepts of digital system and logic design.
  • To gain thorough understanding of hardware description language such as VHDL for designing digital systems.
  • To strengthen the concept of designing complex combinational and sequential logic circuits.
  • To provide hands on experience in simulating digital circuits using CAD tools.
  • To provide facilities to test the circuits on hardware such as FPGA board.


  • Computer system : 22 PCs with 2 servers
  • Simulation Facilities: HEP1 and HEP2 tools from Mentor Graphics (licensed), Xilinx ISE (Freeware).
  • Hardware Facilities: FPGA board Spartan-3


  • Faculty Coordinator: Dr. Monica Gupta
  • Other Faculty Users: Dr. Manoj, Dr. Jyoti
  • Lab Technician: Ms. Asha Saini